US 12,117,886 B2
System, apparatus and method for dynamically adjusting platform power and performance based on task characteristics
Jianfang Zhu, Portland, OR (US); Deepak Samuel Kirubakaran, Hillsboro, OR (US); Raoul Rivas Toledano, Hillsboro, OR (US); Chee Lim Nge, Beaverton, OR (US); Rajshree Chabukswar, Sunnyvale, CA (US); James Hermerding, II, Vancouver, WA (US); Sudheer Nair, Portland, OR (US); William Braun, Beaverton, OR (US); Zhongsheng Wang, Camas, WA (US); Russell Fenger, Beaverton, OR (US); and Udayan Kapaley, Hillsboro, OR (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by INTEL CORPORATION, Santa Clara, CA (US)
Filed on Aug. 15, 2023, as Appl. No. 18/449,890.
Application 18/449,890 is a continuation of application No. 17/879,256, filed on Aug. 2, 2022, granted, now 11,775,047.
Application 17/879,256 is a continuation of application No. 16/830,485, filed on Mar. 26, 2020, granted, now 11,422,616, issued on Aug. 23, 2022.
Prior Publication US 2024/0045490 A1, Feb. 8, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 1/32 (2019.01); G06F 1/3228 (2019.01); G06F 1/329 (2019.01); G06F 9/38 (2018.01); G06F 9/48 (2006.01)
CPC G06F 1/329 (2013.01) [G06F 1/3228 (2013.01); G06F 9/3836 (2013.01); G06F 9/4812 (2013.01); G06F 9/4893 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A processor, comprising:
a plurality of cores including a first plurality of cores and a second plurality of cores, the second plurality of cores comprising relatively lower power cores than the first plurality of cores;
graphics processing circuitry to perform graphics operations;
a memory controller to couple the plurality of cores and the graphics processing circuitry to a memory; and
power control circuitry to control power consumption of the plurality of cores and the graphics processing circuitry, the power control circuitry to determine background task metric information based on a first amount of time that at least one core of the plurality of cores executed background tasks during an active duration, the power control circuitry to dynamically apply a power management policy for a background mode when the background task metric information exceeds a first threshold, the power management policy for the background mode to reduce power consumption of at least the processor.