US 12,117,864 B2
Interface device and signal transceiving method thereof
Bi-Yang Li, Hsinchu (TW); Igor Elkanovich, Hsinchu (TW); Hung-Yi Chang, Hsinchu (TW); and Shih-Cheng Kao, Hsinchu (TW)
Assigned to Global Unichip Corporation, Hsinchu (TW); and Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Global Unichip Corporation, Hsinchu (TW); and Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Sep. 23, 2022, as Appl. No. 17/951,113.
Application 17/951,113 is a continuation in part of application No. 17/859,003, filed on Jul. 7, 2022, abandoned.
Prior Publication US 2024/0012442 A1, Jan. 11, 2024
Int. Cl. G06F 1/08 (2006.01); G06F 1/04 (2006.01); G06F 1/10 (2006.01); G06F 1/12 (2006.01); G06F 13/42 (2006.01); H03K 3/012 (2006.01); H03K 3/037 (2006.01); H03K 5/00 (2006.01); H03K 5/22 (2006.01)
CPC G06F 1/08 (2013.01) [G06F 1/12 (2013.01); H03K 3/012 (2013.01); H03K 3/0372 (2013.01); H03K 5/22 (2013.01); G06F 1/04 (2013.01); G06F 1/10 (2013.01); G06F 13/4217 (2013.01); G06F 13/423 (2013.01); H03K 2005/00019 (2013.01)] 17 Claims
OG exemplary drawing
 
1. An interface device of a semiconductor device, the interface device comprising:
a master device, wherein a master circuit is implemented in the master device; and
a plurality of slave devices, wherein the slave devices are stacked on the master device to form a three-dimensional structure, wherein a slave circuit is implemented in each of the slave devices, and each of the slave circuits are coupled to the master circuit,
wherein each slave circuit comprises:
a first receiver, receiving an input data from the master circuit;
a second receiver, receiving a first clock signal from the master circuit;
a first clock generator, coupled to the second receiver, delaying the first clock signal according to a first delay value to generate a first delayed clock signal, and generating a plurality of first sampling signals according to the first delayed clock signal;
a first sampler, sampling the input data according to the first sampling signals to generate a plurality of first sampling results; and
a first comparator, coupled to the first sampler, and generating a first comparison result by comparing the first sampling results,
wherein the first clock generator adjusts the first delay value according to the first comparison result,
wherein when the first sampling results are not all the same, the first comparator causes the first clock generator to increase the first delay value according to the first comparison result, and when the first sampling results are all the same, the first comparator causes the first clock generator to decrease the first delay value according to the first comparison result.