US 12,117,347 B2
Metrology target design for tilted device designs
Myungjun Lee, San Jose, CA (US); Mark D. Smith, Austin, TX (US); Michael E. Adel, Ya'akov Zichron (IL); Eran Amit, Haifa (IL); and Daniel Kandel, Aseret (IL)
Assigned to KLA Corporation, Milpitas, CA (US)
Filed by KLA Corporation, Milpitas, CA (US)
Filed on Oct. 6, 2016, as Appl. No. 15/287,388.
Application 15/287,388 is a continuation of application No. PCT/US2016/028314, filed on Apr. 19, 2016.
Claims priority of provisional application 62/150,290, filed on Apr. 21, 2015.
Prior Publication US 2017/0023358 A1, Jan. 26, 2017
Int. Cl. G01J 9/00 (2006.01); G03F 7/00 (2006.01); H01L 21/66 (2006.01)
CPC G01J 9/00 (2013.01) [G03F 7/705 (2013.01); G03F 7/70683 (2013.01); H01L 22/30 (2013.01)] 40 Claims
OG exemplary drawing
 
1. A method comprising:
calculating, with at least one processor, a Zernike sensitivity of pattern placement errors (PPEs) of at least one device design and of a plurality of metrology target designs;
selecting, with at least one processor, a best metrology target design according to a value of a cost function derived from the calculated Zernike sensitivities, the cost function quantifying a similarity of the Zernike sensitivity between the at least one device design and the plurality of metrology target designs;
controlling, with at least one processor, a scanner to modify a pattern pitch to produce one or more metrology targets having the best metrology target design on a sample; and
performing, with an overlay metrology tool, one or more overlay metrology measurements of the one or more metrology targets having the best metrology target design.