US 12,446,476 B2
Method for manufacturing a memory resistor device
Anthony Kenyon, London (GB); Adnan Mehonic, London (GB); and Wing Ng, London (GB)
Assigned to UCL Business Ltd., London (GB)
Appl. No. 17/778,383
Filed by UCL Business Ltd., London (GB)
PCT Filed Nov. 20, 2020, PCT No. PCT/GB2020/052967
§ 371(c)(1), (2) Date May 19, 2022,
PCT Pub. No. WO2021/099798, PCT Pub. Date May 27, 2021.
Claims priority of application No. 1917071 (GB), filed on Nov. 22, 2019.
Prior Publication US 2022/0416163 A1, Dec. 29, 2022
Int. Cl. H10N 70/00 (2023.01); H10B 63/00 (2023.01)
CPC H10N 70/023 (2023.02) [H10B 63/80 (2023.02); H10N 70/063 (2023.02); H10N 70/841 (2023.02); H10N 70/883 (2023.02)] 17 Claims
OG exemplary drawing
 
1. A method for manufacturing a memory resistor device, the method comprising:
depositing a first layer of a dielectric material onto a first electrode;
removing a subsection of the first layer of the dielectric material to expose one or more edges of the dielectric material;
depositing a second layer of the dielectric material to create one or more boundaries between the one or more edges of the first layer of the dielectric material and the second layer of the dielectric material; and
providing a second electrode, wherein at least one boundary of the one or more boundaries between the one or more edges of the first layer of the dielectric material and the second layer of the dielectric material intersects with both an edge of the first electrode and an edge of the second electrode.