US 12,446,473 B2
Bottom electrode via and conductive barrier design to eliminate electrical short in memory devices
Chern-Yow Hsu, Chu-Bei (TW); and Shih-Chang Liu, Alian Township (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed on Apr. 30, 2021, as Appl. No. 17/245,221.
Prior Publication US 2022/0352458 A1, Nov. 3, 2022
Int. Cl. H10N 50/80 (2023.01); H10N 50/01 (2023.01); H10N 50/10 (2023.01)
CPC H10N 50/80 (2023.02) [H10N 50/01 (2023.02); H10N 50/10 (2023.02)] 20 Claims
OG exemplary drawing
 
7. A method of forming an integrated chip (IC), comprising:
forming an interconnect structure within a lower inter-level dielectric (ILD) layer over a substrate;
forming a conductive barrier layer onto the interconnect structure;
forming an etch stop layer along an upper surface and outermost sidewalls of the conductive barrier layer;
forming a dielectric material over the lower ILD layer and the conductive barrier layer;
forming a bottom electrode via (BEVA) extending through the dielectric material to the conductive barrier layer;
forming a bottom electrode structure onto topmost surfaces of the bottom electrode via and the dielectric material;
forming a data storage element onto the bottom electrode structure;
forming a top electrode structure over the data storage element;
performing one or more patterning processes on the top electrode structure, the data storage element, the bottom electrode structure, and the dielectric material to form a memory device having a data storage structure between a top electrode and a bottom electrode;
forming a sidewall spacer along outermost sidewalls of the data storage structure, the bottom electrode, and the dielectric material; and
forming an upper dielectric structure onto a sidewall of the sidewall spacer, wherein the sidewall spacer laterally separates the upper dielectric structure from the outermost sidewalls of the data storage structure, the bottom electrode, and the dielectric material and wherein the upper dielectric structure continuously extends from vertically above the topmost surface of the bottom electrode via to vertically below a bottommost surface of the bottom electrode via.