| CPC H10H 20/857 (2025.01) [G09F 9/3026 (2013.01); G09F 9/33 (2013.01); G09G 3/32 (2013.01); H01L 25/0753 (2013.01); H10H 20/831 (2025.01); H10H 29/142 (2025.01); G09G 2310/0275 (2013.01)] | 32 Claims |
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1. A display device comprising:
a plurality of sub-pixels arranged in a display area;
an active layer disposed on a substrate;
a gate insulating layer overlapping the active layer in a plan view;
a first interlayer insulating layer overlapping a first conductive layer disposed on the gate insulating layer in a plan view;
a second interlayer insulating layer overlapping a second conductive layer disposed on the first interlayer insulating layer in a plan view;
a first planarization layer overlapping a third conductive layer disposed on the second interlayer insulating layer in a plan view;
a second planarization layer overlapping a fourth conductive layer disposed on the first planarization layer in a plan view;
a third planarization layer overlapping a fifth conductive layer disposed on the second planarization layer in a plan view;
a sixth conductive layer disposed on the third planarization layer; and
a seventh conductive layer disposed on at least part of the sixth conductive layer, wherein
the sixth conductive layer comprises:
a plurality of anode electrodes respectively corresponding to the plurality of sub-pixels;
a plurality of cathode electrodes respectively corresponding to the plurality of sub-pixels and respectively spaced apart from the plurality of anode electrodes; and
a cathode line electrically connected to the plurality of cathode electrodes, and the seventh conductive layer comprises:
a plurality of anode pads respectively overlapping the plurality of anode electrodes in a plan view;
a plurality of cathode pads respectively overlapping the plurality of cathode electrodes in a plan view; and
a cathode line pad overlapping at least part of the cathode line in a plan view.
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