US 12,446,377 B2
Semiconductor device
Hiroyuki Miyahara, Tokyo (JP); Hisayoshi Motobayashi, Tokyo (JP); Yoshiro Takiguchi, Tokyo (JP); Takahiro Koyama, Tokyo (JP); and Hidekazu Kawanishi, Toyko (JP)
Assigned to Sony Group Corporation, Tokyo (JP)
Appl. No. 17/770,700
Filed by Sony Group Corporation, Tokyo (JP)
PCT Filed Oct. 8, 2020, PCT No. PCT/JP2020/038208
§ 371(c)(1), (2) Date Apr. 21, 2022,
PCT Pub. No. WO2021/085071, PCT Pub. Date May 6, 2021.
Claims priority of application No. 2019-195148 (JP), filed on Oct. 28, 2019.
Prior Publication US 2022/0376156 A1, Nov. 24, 2022
Int. Cl. H01L 33/62 (2010.01); H10H 20/85 (2025.01); H10H 20/857 (2025.01)
CPC H10H 20/857 (2025.01) [H10H 20/8506 (2025.01)] 16 Claims
OG exemplary drawing
 
1. A semiconductor device comprising:
a semiconductor element;
a first housing member and a second housing member that house the semiconductor element;
a first base layer formed on a first bonded surface of the first housing member to the second housing member;
a second base layer formed on a second bonded surface of the second housing member to the first housing member, the first bonded surface facing the second bonded surface, and the first bonded surface and the second bonded surface are spaced away from each other in a first direction;
a solder bonding section that bonds the first housing member and the second housing member with the first base layer and the second base layer interposed in between; and
a solder adsorption layer
provided between the first bonded surface and the second bonded surface in the first direction and on at least one of the first bonded surface or the second bonded surface,
spaced apart from the first base layer and the second base layer in a second direction that intersects the first direction, and
unopposed by the first base layer, the second base layer, and any other base layer in the first direction.