US 12,446,350 B2
Stacked light-receiving sensor and in-vehicle imaging device
Ryoji Eki, Kanagawa (JP)
Assigned to Sony Semiconductor Solutions Corporation, Kanagawa (JP)
Filed by Sony Semiconductor Solutions Corporation, Kanagawa (JP)
Filed on Aug. 1, 2023, as Appl. No. 18/363,332.
Application 18/363,332 is a continuation of application No. 17/262,691, abandoned, previously published as PCT/JP2019/030093, filed on Jul. 31, 2019.
Claims priority of application No. 2018-143973 (JP), filed on Jul. 31, 2018; application No. 2019-139439 (JP), filed on Jul. 30, 2019; and application No. 2019-139481 (JP), filed on Jul. 30, 2019.
Prior Publication US 2024/0021646 A1, Jan. 18, 2024
Int. Cl. H01L 27/146 (2006.01); G06F 18/214 (2023.01); G06N 3/04 (2023.01); G06V 10/147 (2022.01); G06V 10/764 (2022.01); G06V 10/82 (2022.01); G06V 20/58 (2022.01); G06V 20/59 (2022.01); H04N 7/18 (2006.01); H04N 23/617 (2023.01); H04N 25/44 (2023.01); H04N 25/709 (2023.01); H04N 25/75 (2023.01); H04N 25/79 (2023.01); H10F 39/00 (2025.01)
CPC H10F 39/809 (2025.01) [G06F 18/214 (2023.01); G06N 3/04 (2013.01); G06V 10/147 (2022.01); G06V 10/764 (2022.01); G06V 10/82 (2022.01); G06V 20/58 (2022.01); G06V 20/584 (2022.01); G06V 20/597 (2022.01); H04N 7/18 (2013.01); H04N 23/617 (2023.01); H04N 25/44 (2023.01); H04N 25/709 (2023.01); H04N 25/75 (2023.01); H04N 25/79 (2023.01); H10F 39/811 (2025.01)] 14 Claims
OG exemplary drawing
 
1. A stacked light-receiving sensor comprising:
a first substrate having a plurality of sides and a center; and
a second substrate bonded to the first substrate,
the first substrate including:
a pixel array in which a plurality of unit pixels are arranged in a two-dimensional matrix and the plurality of pixels are positioned more proximate to one of the plurality of sides of the first substrate than the center of the first substrate, and
a plurality of vias positioned between the one of the plurality of sides of the first substrate and the pixel array;
the second substrate including:
a converter configured to convert an analog pixel signal output from the pixel array to digital image data signal and
a processor configured to perform a process based on a neural network calculation model for data based on the digital image data signal, wherein
the converter is overlapped with the pixel array in a stacking direction of the first substrate and the second substrate,
the plurality of pixels in the pixel array are electrically connected to the converter by the plurality of vias, and
the processor is not overlapped with the pixel array in the stacking direction.