US 12,446,349 B2
Photoelectric conversion device, image pickup system and method of manufacturing photoelectric conversion device
Mineo Shimotsusa, Machida (JP); Takeshi Ichikawa, Hachioji (JP); and Yasuhiro Sekine, Yokohama (JP)
Assigned to Canon Kabushiki Kaisha, Tokyo (JP)
Filed by CANON KABUSHIKI KAISHA, Tokyo (JP)
Filed on Aug. 2, 2022, as Appl. No. 17/816,844.
Application 14/514,090 is a division of application No. 13/774,150, filed on Feb. 22, 2013, granted, now 8,890,331, issued on Nov. 18, 2014.
Application 17/816,844 is a continuation of application No. 16/719,651, filed on Dec. 18, 2019, granted, now 11,437,421.
Application 16/719,651 is a continuation of application No. 15/849,403, filed on Dec. 20, 2017, granted, now 10,546,891, issued on Jan. 28, 2020.
Application 15/849,403 is a continuation of application No. 15/155,931, filed on May 16, 2016, granted, now 9,881,957, issued on Jan. 30, 2018.
Application 15/155,931 is a continuation of application No. 14/685,337, filed on Apr. 13, 2015, granted, now 9,368,544, issued on Jun. 14, 2016.
Application 14/685,337 is a continuation of application No. 14/514,090, filed on Oct. 14, 2014, granted, now 9,029,241, issued on May 12, 2015.
Claims priority of application No. 2012-043962 (JP), filed on Feb. 29, 2012.
Prior Publication US 2022/0375981 A1, Nov. 24, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. H10F 39/00 (2025.01); H01L 23/00 (2006.01); H10F 77/60 (2025.01)
CPC H10F 39/809 (2025.01) [H01L 24/05 (2013.01); H10F 39/018 (2025.01); H10F 39/026 (2025.01); H10F 39/804 (2025.01); H10F 39/8053 (2025.01); H10F 77/60 (2025.01); H01L 2224/02166 (2013.01); H01L 2224/04042 (2013.01); H01L 2224/48463 (2013.01); H01L 2924/12042 (2013.01); H01L 2924/12043 (2013.01); H01L 2924/13091 (2013.01); H01L 2924/351 (2013.01)] 24 Claims
OG exemplary drawing
 
1. A method of manufacturing a semiconductor device, comprising:
preparing a composite member including a first semiconductor wafer, a second semiconductor wafer, a conductor layer, an insulator layer and a semiconductor element, wherein, in the composite member, the second semiconductor wafer is stacked on the first semiconductor wafer, the conductor layer and the insulator layer are interposed between the first semiconductor wafer and the second semiconductor wafer, and the semiconductor element is provided on a surface of the second semiconductor wafer;
dividing the composite member; and
thinning the second semiconductor wafer before the dividing,
wherein, in the dividing, a thickness of the second semiconductor wafer is greater than a distance from the surface of the second semiconductor wafer to a back surface of the first semiconductor wafer, the back surface being disposed at a side opposite to a side at which the second semiconductor wafer is disposed.