US 12,446,326 B2
Charging protection circuit, charging circuit, and electronic device
Huaifeng Wang, Shenzhen (CN); Jiangtao Yang, Shanghai (CN); and Hang Wang, Dongguan (CN)
Assigned to Huawei Technologies Co., Ltd., Shenzhen (CN)
Filed by HUAWEI TECHNOLOGIES CO., LTD., Guangdong (CN)
Filed on Apr. 29, 2024, as Appl. No. 18/649,658.
Application 18/649,658 is a continuation of application No. 17/852,476, filed on Jun. 29, 2022, granted, now 12,002,801.
Application 17/852,476 is a continuation of application No. PCT/CN2020/138470, filed on Dec. 23, 2020.
Claims priority of application No. 201911398178.5 (CN), filed on Dec. 30, 2019; and application No. 202010616212.8 (CN), filed on Jun. 30, 2020.
Prior Publication US 2024/0355811 A1, Oct. 24, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. H10D 89/60 (2025.01); H02H 9/04 (2006.01); H03K 19/003 (2006.01)
CPC H10D 89/814 (2025.01) [H02H 9/046 (2013.01); H03K 19/00315 (2013.01); H10D 89/611 (2025.01); H10D 89/815 (2025.01)] 19 Claims
OG exemplary drawing
 
1. A charging protection circuit, comprising:
a first four-terminal N-type metal oxide semiconductor NMOS switching transistor, comprising a first drain, a second drain, a gate, and a Sub port, wherein the first drain is connected to a first power supply interface, the second drain is connected to a load, and the gate is connected to a drive circuit; and
a Sub port management circuit, comprising a pull-up circuit connected to the Sub port, wherein the pull-up circuit is configured to: when the first four-terminal NMOS switching transistor is turned on, pull up potential of the Sub port to a potential of the first drain or the second drain, wherein the pull-up circuit comprises a first three-terminal NMOS switching transistor; and
a drain of the first three-terminal NMOS switching transistor is connected to the first drain of the first four-terminal NMOS switching transistor, a source of the first three-terminal NMOS switching transistor is connected to the Sub port, a gate of the first three-terminal NMOS switching transistor is connected to the drive circuit, and a drive voltage provided by the drive circuit enables both the first three-terminal NMOS switching transistor and the first four-terminal NMOS switching transistor to be turned on,
wherein the drive circuit is configured to provide a same drive voltage for the gate of the first four-terminal NMOS switching transistor and the gate of the first three-terminal NMOS switching transistor.