| CPC H10D 89/811 (2025.01) [H10D 89/921 (2025.01)] | 15 Claims |

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1. A device for ESD protection comprising:
a current limiting resistor with a first node coupled to a pad and a second node coupled to an isolation n-well;
a protection transistor located in a p-well inside the isolation n-well, the protection transistor including:
a source node coupled to the pad;
a gate node coupled to the pad, and
a bulk node coupled to the pad;
a protection clamp located outside the isolation n-well, the protection clamp having a cathode coupled to a drain node of the protection transistor and an anode coupled to ground.
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