| CPC H10D 89/811 (2025.01) [H10D 84/85 (2025.01)] | 20 Claims |
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1. A semiconductor ESD protection device comprising:
a pair of source regions;
a pair of gate structures disposed between the pair of source regions and extending along a direction;
a drain region disposed between the pair of gate structures;
a plurality of first conductive contacts disposed on the source regions and arranged along the direction;
a plurality of second conductive contacts disposed on the gate structures;
a plurality of third conductive contacts disposed on the drain region and arranged along the direction; and
a dummy structure disposed over the drain region and between the gate structures and between the third conductive contacts.
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