US 12,446,322 B2
Electrostatic discharge protection devices including a silicon-controlled rectifier
Prantik Mahajan, Dresden (DE); Ajay, Aligarh (IN); Vishal Ganesan, Dresden (DE); Ruchil Jain, Dresden (DE); and Souvick Mitra, Essex Junction, VT (US)
Assigned to GlobalFoundries U.S. Inc., Malta, NY (US)
Filed by GlobalFoundries U.S. Inc., Malta, NY (US)
Filed on Apr. 20, 2022, as Appl. No. 17/724,548.
Prior Publication US 2023/0343778 A1, Oct. 26, 2023
Int. Cl. H10D 84/85 (2025.01); H10D 89/60 (2025.01)
CPC H10D 89/713 (2025.01) [H10D 84/859 (2025.01)] 19 Claims
OG exemplary drawing
 
1. A structure for an electrostatic discharge protection device, the structure comprising:
a semiconductor substrate having a top surface;
a first shallow trench isolation region in the semiconductor substrate;
a second shallow trench isolation region in the semiconductor substrate, the second shallow trench isolation region adjacent to the first shallow trench isolation region;
a third shallow trench isolation region in the semiconductor substrate, the third shallow trench isolation region adjacent to the second shallow trench isolation region;
a first well in the semiconductor substrate, the first well having a first conductivity type;
a second well and a third well in the first well, the second well and the third well having the first conductivity type;
a fourth well in the first well, the fourth well positioned in a lateral direction between the second well and the third well, and the fourth well having a second conductivity type opposite to the first conductivity type;
a first doped region in the second well, the first doped region having the first conductivity type, and the first doped region having a higher dopant concentration than the second well;
a second doped region in the second well, the second doped region having the second conductivity type, and the second doped region spaced in the lateral direction from the first doped region by a gap;
a third doped region in the fourth well, the third doped region having the second conductivity type;
a fourth doped region in the fourth well, the fourth doped region having the first conductivity type; and
a first electrical connection coupled to the third doped region and the fourth doped region,
wherein the first doped region and the second doped region are positioned in the lateral direction between the first shallow trench isolation region and the second shallow trench isolation region, the second well, the third well, and the fourth well are positioned in a vertical direction between the first well and the top surface of the semiconductor substrate, the second shallow trench isolation region is positioned in the lateral direction between the first doped region and the third doped region, and the third shallow trench isolation region is positioned in the lateral direction between the third doped region and the fourth doped region.