	US 12,446,321 B2
	Circuits designed and manufactured with first and second fin boundaries
Chung-Hui Chen, Hsinchu (TW); Weichih Chen, Hsinchu (TW); Tien-Chien Huang, Hsinchu (TW); Chien-Chun Tsai, Jhudong Township (TW); Ruey-Bin Sheen, Taichung (TW); Tsung-Hsin Yu, Hsinchu (TW); Chih-Hsien Chang, New Taipei (TW); and Cheng-Hsiang Hsieh, Taipei (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Dec. 6, 2021, as Appl. No. 17/543,255.
Claims priority of provisional application 63/166,116, filed on Mar. 25, 2021.
Claims priority of provisional application 63/154,270, filed on Feb. 26, 2021.
Prior Publication US 2022/0278091 A1, Sep. 1, 2022
Int. Cl. H10D 89/10 (2025.01); H10D 30/62 (2025.01); H10D 64/01 (2025.01); H10D 84/01 (2025.01); H10D 84/03 (2025.01); H10D 84/83 (2025.01); H03K 17/687 (2006.01)

CPC H10D 89/10 (2025.01) [H10D 30/6219 (2025.01); H10D 64/01 (2025.01); H10D 84/0158 (2025.01); H10D 84/038 (2025.01); H10D 84/834 (2025.01); H03K 17/6871 (2013.01)]

20 Claims

1. A semiconductor structure, comprising:

first finfet cells, each of the first finfet cells having an analog fin boundary according to analog circuit design rules;

second finfet cells, each of the second finfet cells having a digital fin boundary according to digital circuit design rules;

first circuits formed with the first finfet cells;

second circuits formed with the second finfet cells; and

third circuits formed with one or more of the first finfet cells and one or more of the second finfet cells,

wherein the second finfet cells include layers that include a plurality of via-over-diffusion contacts including a first via-over-diffusion contact having a first size to provide a first resistance and a second via-over-diffusion contact having a second size that is greater than the first size to provide a second resistance that is less than or equal to 0.5 times the first resistance of the first via-over-drain contact.