US 12,446,320 B2
Bottom contact with self-aligned spacer for stacked semiconductor devices
Gen Tsutsui, Glenmont, NY (US); Albert M. Young, Fishkill, NY (US); Su Chen Fan, Cohoes, NY (US); Junli Wang, Slingerlands, NY (US); and Brent A Anderson, Jericho, VT (US)
Assigned to International Business Machines Corporation, Armonk, NY (US)
Filed by International Business Machines Corporation, Armonk, NY (US)
Filed on Mar. 22, 2022, as Appl. No. 17/655,807.
Prior Publication US 2023/0307447 A1, Sep. 28, 2023
Int. Cl. H10D 88/00 (2025.01); H10D 64/01 (2025.01); H10D 64/23 (2025.01); H10D 84/85 (2025.01)
CPC H10D 88/00 (2025.01) [H10D 64/01 (2025.01); H10D 64/251 (2025.01); H10D 84/85 (2025.01)] 16 Claims
OG exemplary drawing
 
1. A semiconductor structure composed of stacked semiconductor devices, the semiconductor structure comprising:
a top semiconductor device on a dielectric material layer, wherein the top semiconductor device is encapsulated in a top interlayer dielectric;
a bottom semiconductor device under the top semiconductor device, wherein the bottom semiconductor device is wider than the top semiconductor device, wherein the bottom semiconductor device includes a layer of epitaxy on a portion of a top surface of the bottom semiconductor device and a vertical side of the bottom semiconductor device, wherein the layer of epitaxy is between the bottom semiconductor device and a bottom contact, wherein a top surface of the layer of epitaxy is wider than a bottom surface of the layer of epitaxy; and
the bottom contact connecting to a portion of the top surface and the vertical side of the bottom semiconductor device.