US 12,446,309 B2
Display device and electronic device
Susumu Kawashima, Kanagawa (JP); and Naoto Kusumoto, Kanagawa (JP)
Assigned to Semiconductor Energy Laboratory Co., Ltd., Atsugi (JP)
Filed by SEMICONDUCTOR ENERGY LABORATORY CO., LTD., Atsugi (JP)
Filed on Mar. 13, 2024, as Appl. No. 18/603,286.
Application 18/603,286 is a continuation of application No. 18/205,587, filed on Jun. 5, 2023, granted, now 11,935,897.
Application 18/205,587 is a continuation of application No. 17/507,005, filed on Oct. 21, 2021, granted, now 11,715,740, issued on Aug. 1, 2023.
Application 17/507,005 is a continuation of application No. 16/755,645, granted, now 11,189,643, issued on Nov. 30, 2021, previously published as PCT/IB2018/058354, filed on Oct. 26, 2018.
Claims priority of application No. 2017-212645 (JP), filed on Nov. 2, 2017.
Prior Publication US 2025/0081612 A1, Mar. 6, 2025
Int. Cl. G02F 1/1362 (2006.01); H10D 86/40 (2025.01); H10D 86/60 (2025.01); H10K 59/131 (2023.01); H10K 59/80 (2023.01)
CPC H10D 86/423 (2025.01) [G02F 1/13624 (2013.01); H10D 86/441 (2025.01); H10D 86/481 (2025.01); H10D 86/60 (2025.01); H10K 59/131 (2023.02); H10K 59/8722 (2023.02)] 8 Claims
OG exemplary drawing
 
1. A display device comprising:
a first transistor; and
a plurality of pixels, each of the plurality of pixels comprising:
a second transistor;
a third transistor;
a fourth transistor;
a fifth transistor;
a first capacitor;
a second capacitor; and
an EL element,
wherein one of a source and a drain of the first transistor is electrically connected to a first wiring,
wherein the other of the source and the drain of the first transistor is directly connected to one electrode of the first capacitor in a first pixel of the plurality of pixels, one electrode of the first capacitor in a second pixel of the plurality of pixels, and one electrode of the first capacitor in a third pixel of the plurality of pixels,
wherein, in the first pixel, one of a source and a drain of the second transistor is electrically connected to a second wiring,
wherein, in the first pixel, a gate of the second transistor is electrically connected to a third wiring,
wherein, in the first pixel, the other of the source and the drain of the second transistor is directly connected to the other electrode of the first capacitor, one electrode of the second capacitor, and a gate of the third transistor,
wherein, in the first pixel, one of a source and a drain of the third transistor is electrically connected to one of a source and a drain of the fourth transistor and one of a source and a drain of the fifth transistor,
wherein, in the first pixel, a gate of the fourth transistor is electrically connected to a fourth wiring,
wherein, in the first pixel, a gate of the fifth transistor is electrically connected to a fifth wiring,
wherein, in the first pixel, the other of the source and the drain of the fourth transistor is electrically connected to one electrode of the EL element, and
wherein, in the first pixel, a channel formation region of the second transistor comprises an oxide semiconductor.