US 12,446,306 B2
Stacked field effect transistor structure with independent gate control between top and bottom gates
Tsung-Sheng Kang, Ballston Lake, NY (US); Su Chen Fan, Cohoes, NY (US); Jingyun Zhang, Albany, NY (US); Ruqiang Bao, Niskayuna, NY (US); and Son Nguyen, Schenectady, NY (US)
Assigned to International Business Machines Corporation, Armonk, NY (US)
Filed by INTERNATIONAL BUSINESS MACHINES CORPORATION, Armonk, NY (US)
Filed on Oct. 26, 2022, as Appl. No. 18/050,032.
Prior Publication US 2024/0145473 A1, May 2, 2024
Int. Cl. H10D 84/85 (2025.01); H10D 30/01 (2025.01); H10D 30/43 (2025.01); H10D 30/67 (2025.01); H10D 62/10 (2025.01); H10D 64/01 (2025.01); H10D 84/01 (2025.01); H10D 84/03 (2025.01); H10D 88/00 (2025.01)
CPC H10D 84/856 (2025.01) [H10D 30/014 (2025.01); H10D 30/031 (2025.01); H10D 30/43 (2025.01); H10D 30/6729 (2025.01); H10D 30/6735 (2025.01); H10D 62/121 (2025.01); H10D 64/017 (2025.01); H10D 84/0167 (2025.01); H10D 84/0186 (2025.01); H10D 84/0188 (2025.01); H10D 84/038 (2025.01); H10D 88/01 (2025.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor device, comprising:
a first transistor;
a first gate electrically coupled to the first transistor;
a dielectric isolation layer on top of at least a portion of the first transistor;
a second transistor on top of at least a portion of the dielectric isolation layer;
a second gate electrically coupled to the second transistor, wherein the dielectric isolation layer is disposed to isolate the first gate from the second gate; and
a first conductive contact electrically coupled to the first gate, wherein the first conductive contact is within a first lateral boundary of the first transistor and outside of a second lateral boundary of the second transistor.