US 12,446,305 B2
Uniform gate width for nanostructure devices
Jui-Chien Huang, Hsinchu (TW); Shih-Cheng Chen, New Taipei (TW); Chih-Hao Wang, Hsinchu County (TW); Kuo-Cheng Chiang, Hsinchu County (TW); Zhi-Chang Lin, Hsinchu County (TW); Jung-Hung Chang, Hsinchu (TW); Lo-Heng Chang, Hsinchu (TW); Shi Ning Ju, Hsinchu (TW); and Guan-Lin Chen, Hsinchu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsin-Chu (TW)
Filed on Nov. 29, 2023, as Appl. No. 18/522,687.
Application 18/522,687 is a continuation of application No. 17/728,247, filed on Apr. 25, 2022, granted, now 11,855,096.
Application 17/728,247 is a continuation of application No. 16/932,476, filed on Jul. 17, 2020, granted, now 11,315,925, issued on Apr. 26, 2022.
Claims priority of provisional application 62/894,325, filed on Aug. 30, 2019.
Claims priority of provisional application 62/892,661, filed on Aug. 28, 2019.
Prior Publication US 2024/0096895 A1, Mar. 21, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 27/092 (2006.01); H01L 29/06 (2006.01); H10D 30/01 (2025.01); H10D 30/62 (2025.01); H10D 62/10 (2025.01); H10D 64/01 (2025.01); H10D 84/01 (2025.01); H10D 84/03 (2025.01); H10D 84/85 (2025.01)
CPC H10D 84/853 (2025.01) [H10D 30/0245 (2025.01); H10D 30/6211 (2025.01); H10D 62/118 (2025.01); H10D 64/021 (2025.01); H10D 84/0128 (2025.01); H10D 84/0158 (2025.01); H10D 84/038 (2025.01)] 20 Claims
OG exemplary drawing
 
1. A device comprising:
a plurality of semiconductor layers disposed on a substrate, wherein the plurality of semiconductor layers includes a first semiconductor layer, a second semiconductor layer and a third semiconductor layer;
a gate structure disposed on each of the semiconductor layers such that a thickness of the gate structure between each semiconductor layer varies, wherein the gate structure includes a first gate region between the first and second semiconductor layers and a second gate region extending between the second and third semiconductor layers, wherein a width of the first gate region is substantially the same as a width of the second gate region; and
a first sidewall spacer disposed along the first gate region and a second sidewall spacer disposed along the second gate region, the first sidewall spacer having a first width and the second sidewall spacer having a second width that is different than the first width.