US 12,446,303 B2
Stacking CMOS structure
Yu-Xuan Huang, Hsinchu (TW); Chia-En Huang, Hsinchu County (TW); Ching-Wei Tsai, Hsinchu (TW); and Kuan-Lun Cheng, Hsin-Chu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed on May 23, 2024, as Appl. No. 18/672,936.
Application 18/672,936 is a continuation of application No. 17/116,552, filed on Dec. 9, 2020, granted, now 11,996,409.
Claims priority of provisional application 63/027,811, filed on May 20, 2020.
Prior Publication US 2024/0312995 A1, Sep. 19, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 27/092 (2006.01); H01L 21/8238 (2006.01); H01L 23/528 (2006.01); H01L 29/06 (2006.01); H01L 29/423 (2006.01); H10D 30/67 (2025.01); H10D 62/10 (2025.01); H10D 84/01 (2025.01); H10D 84/03 (2025.01); H10D 84/85 (2025.01)
CPC H10D 84/85 (2025.01) [H01L 23/5286 (2013.01); H10D 30/6735 (2025.01); H10D 62/118 (2025.01); H10D 84/0188 (2025.01); H10D 84/038 (2025.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor structure, comprising:
a first source/drain feature;
an isolation feature disposed over the first source/drain feature;
a second source/drain feature disposed over the isolation feature, where the first and the second source/drain features are of opposite conductivity types;
a third source/drain feature;
a fourth source/drain feature disposed over the third source/drain feature, wherein the third source/drain feature directly contacts the fourth source/drain feature, where the third and the fourth source/drain features are of opposite conductivity types;
a first channel layer connecting the first and the third source/drain features;
a second channel layer over the first channel layer and connecting the second and the fourth source/drain features; and
a gate electrode engaging both the first and the second channel layers.