US 12,446,302 B2
Method for forming capacitor, semiconductor device, module, and electronic device
Tetsuhiro Tanaka, Kiyose (JP); and Yutaka Okazaki, Isehara (JP)
Assigned to Semiconductor Energy Laboratory Co., Ltd., Atsugi (JP)
Filed by Semiconductor Energy Laboratory Co., Ltd., Atsugi (JP)
Filed on Nov. 27, 2023, as Appl. No. 18/519,200.
Application 17/216,759 is a division of application No. 15/991,195, filed on May 29, 2018, granted, now 10,971,491, issued on Apr. 6, 2021.
Application 15/991,195 is a division of application No. 15/298,306, filed on Oct. 20, 2016, granted, now 10,002,866, issued on Jun. 19, 2018.
Application 18/519,200 is a continuation of application No. 17/216,759, filed on Mar. 30, 2021, abandoned.
Claims priority of application No. 2015-214050 (JP), filed on Oct. 30, 2015.
Prior Publication US 2024/0105713 A1, Mar. 28, 2024
Int. Cl. H10D 84/80 (2025.01); H01G 4/008 (2006.01); H01G 4/10 (2006.01); H01G 4/40 (2006.01); H05K 1/18 (2006.01); H10D 1/66 (2025.01); H10D 30/01 (2025.01); H10D 30/67 (2025.01); H10D 86/40 (2025.01); H10D 86/60 (2025.01); H10B 41/70 (2023.01); H10D 84/08 (2025.01); H10D 88/00 (2025.01)
CPC H10D 84/813 (2025.01) [H01G 4/008 (2013.01); H01G 4/105 (2013.01); H01G 4/40 (2013.01); H05K 1/18 (2013.01); H10D 1/66 (2025.01); H10D 30/021 (2025.01); H10D 30/6734 (2025.01); H10D 30/6755 (2025.01); H10D 30/6757 (2025.01); H10D 86/423 (2025.01); H10D 86/481 (2025.01); H10D 86/60 (2025.01); H05K 2201/10015 (2013.01); H05K 2201/10083 (2013.01); H05K 2201/10166 (2013.01); H10B 41/70 (2023.02); H10D 84/08 (2025.01); H10D 84/811 (2025.01); H10D 88/00 (2025.01)] 6 Claims
OG exemplary drawing
 
1. A semiconductor device comprising:
a first transistor comprising silicon in a channel formation region;
a second transistor comprising an oxide semiconductor in a channel formation region; and
a capacitor,
wherein a gate electrode of the first transistor, one of a source region and a drain region of the second transistor, and one electrode of the capacitor are electrically connected to one another,
wherein the semiconductor device further comprises:
a first insulating layer over the channel formation region of the first transistor;
a first conductive layer in direct contact with a top surface of the first insulating layer and serving as a first gate electrode of the second transistor;
a second conductive layer in direct contact with the top surface of the first insulating layer and comprising a same material as the first conductive layer;
an oxide semiconductor layer over the first conductive layer and comprising the channel formation region of the second transistor;
a third conductive layer over the oxide semiconductor layer and serving as a second gate electrode of the second transistor;
a second insulating layer over the third conductive layer;
a fourth conductive layer in direct contact with a top surface of the second insulating layer and electrically connected to the one of the source region and the drain region of the second transistor and to the gate electrode of the first transistor;
a fifth conductive layer in direct contact with the top surface of the second insulating layer and electrically connected to the other of the source region and the drain region of the second transistor and to one of a source region and a drain region of the first transistor;
a sixth conductive layer in direct contact with the top surface of the second insulating layer and electrically connected to the second conductive layer;
a third insulating layer in direct contact with a top surface of the fourth conductive layer, a top surface of the fifth conductive layer, and a top surface of the sixth conductive layer; and
a seventh conductive layer over the third insulating layer,
wherein the fourth conductive layer, the fifth conductive layer, and the sixth conductive layer comprise a same material, and
wherein the seventh conductive layer is electrically connected to the second conductive layer through the sixth conductive layer.