US 12,446,301 B2
Semiconductor integrated circuit device
Isaya Sobue, Yokohama (JP)
Assigned to Socionext Inc., Kanagawa (JP)
Filed by Socionext Inc., Kanagawa (JP)
Filed on Sep. 2, 2022, as Appl. No. 17/902,537.
Application 17/902,537 is a continuation of application No. PCT/JP2021/008218, filed on Mar. 3, 2021.
Claims priority of application No. 2020-041830 (JP), filed on Mar. 11, 2020.
Prior Publication US 2022/0415885 A1, Dec. 29, 2022
Int. Cl. H01L 27/07 (2006.01); H01L 23/528 (2006.01); H01L 29/06 (2006.01); H01L 29/775 (2006.01); H01L 29/786 (2006.01); H10D 30/43 (2025.01); H10D 30/67 (2025.01); H10D 62/10 (2025.01); H10D 84/80 (2025.01)
CPC H10D 84/813 (2025.01) [H01L 23/5283 (2013.01); H10D 30/43 (2025.01); H10D 30/6757 (2025.01); H10D 62/121 (2025.01)] 15 Claims
OG exemplary drawing
 
1. A semiconductor integrated circuit device comprising a capacitive element, the capacitive element having at least one capacitive structure provided between a first node and a second node,
wherein
the capacitive structure includes:
a first transistor having a first nanosheet extending in a first direction and a first gate interconnect extending in a second direction perpendicular to the first direction formed to surround a periphery of the first nanosheet in the second direction and a third direction perpendicular to the first and second directions; and
a second transistor having a second nanosheet extending in the first direction and a second gate interconnect extending in the second direction formed to surround a periphery of the second nanosheet in the second and third directions,
the first and second transistors are adjacent to each other in the second direction and mutually connected at at least one node, and
the first nanosheet and the second nanosheet are opposed to each other in the second direction, a face of the first nanosheet closer to the second nanosheet is exposed from the first gate interconnect, and a face of the second nanosheet closer to the first nanosheet is exposed from the second gate interconnect.