| CPC H10D 84/151 (2025.01) [H01L 21/76202 (2013.01); H01L 21/76224 (2013.01); H10D 1/66 (2025.01); H10D 30/0281 (2025.01)] | 21 Claims |

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1. A capacitor configured for integration with at least one metal-oxide-semiconductor field-effect transistor (MOSFET) device formed on a same substrate, the capacitor comprising:
a first plate comprising a doped semiconductor layer of a first conductivity type;
an insulating layer formed on at least a portion of an upper surface of the doped semiconductor layer;
a second plate comprising a polysilicon layer formed on at least a portion of an upper surface of the insulating layer, wherein an inversion layer is formed in the doped semiconductor layer, beneath at least a portion of the insulating layer and proximate the upper surface of the doped semiconductor layer, as a function of an applied voltage between the first and second plates of the capacitor; and
at least one doped region of a second conductivity type formed in the doped semiconductor layer proximate the upper surface of the doped semiconductor layer and adjacent to one of a drain region and a source region of the first conductivity type formed in the MOSFET device, the doped region being electrically connected to the inversion layer, the second conductivity type being opposite in polarity to the first conductivity type.
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