| CPC H10D 84/138 (2025.01) [H10D 84/401 (2025.01)] | 15 Claims |
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1. A low voltage triggering silicon controlled rectifier, comprising:
an N well and a P well formed on a semiconductor substrate, wherein a second side of the N well and a first side of the P well are in contact to form a PN junction;
a first P+ region formed in a selected region of the N well, wherein the first P+ region is connected to an anode, wherein the anode comprises a metal layer;
a first N+ region formed in a selected region of the P well, wherein the first N+ region is connected to a cathode, wherein the cathode comprises a metal layer;
a silicon controlled rectifier formed by the first P+ region, the N well, the P well and the first N+ region between the anode and the cathode;
a second P+ region formed in a selected region of the N well at the PN junction, wherein the second P+ region extends into the P well by crossing the PN junction;
a second N+ region formed in a selected region of the P well at the PN junction, wherein the second N+ region extends into the N well by crossing the PN junction; wherein the second P+ region and the second N+ region are isolated by a first field oxide;
a first gate structure formed at a surface of the N well between the first P+ region and the second P+ region, wherein the first gate structure is formed by superimposing a first gate dielectric layer and a first gate conductive material layer, wherein the first gate conductive material layer is connected to the anode;
a GDPMOS made of the first P+ region, the first gate structure, the second P+ region and the N well between the first P+ region and the second P+ region, wherein the first P+ region forms a source region of the GDPMOS and the second P+ region forms a drain region of the GDPMOS;
a second gate structure formed at a surface of the P well between the first N+ region and the second N+ region, wherein the second gate structure is formed by superimposing a second gate dielectric layer and a second gate conductive material layer, wherein the second gate conductive material layer is connected to the cathode;
a GGNMOS made of the first N+ region, the second gate structure, the second N+ region and the P well between the first N+ region and the second N+ region; and wherein the first N+ region forms a source region of the GGNMOS and the second N+ region forms a drain region of the GGNMOS;
wherein the silicon controlled rectifier, the GDPMOS and the GGNMOS constitute the low voltage triggering silicon controlled rectifier;
a P+N junction formed of the drain region of the GDPMOS and the N well; and
a N+P junction formed of the drain region of the GGNMOS and the P well;
wherein the P+N junction and the N+P junction work together as a trigger structure for conducting the low voltage triggering silicon controlled rectifier to adjust and reduce a trigger voltage;
and
a conduction path of the low voltage triggering silicon controlled rectifier comprises a first conduction path between the source region and the drain region of the GDPMOS, a second conduction path between the source region and the drain region of the GGNMOS, and a third conduction path of the silicon controlled rectifier, wherein shunting is performed for the first conduction path and the second conduction path to reduce a current in the third conduction path, wherein a holding voltage of the silicon controlled rectifier can be adjusted and boosted.
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