| CPC H10D 84/038 (2025.01) [H01L 21/76802 (2013.01); H01L 21/76877 (2013.01); H01L 23/5226 (2013.01); H10D 30/6735 (2025.01); H10D 30/6757 (2025.01); H10D 64/01 (2025.01); H10D 84/0149 (2025.01)] | 20 Claims |
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1. A device, comprising:
source/drain epitaxial structures over a substrate;
source/drain contacts over the source/drain epitaxial structures, respectively;
a gate structure laterally between the source/drain contacts;
gate spacers spacing apart the gate structure from the source/drain contacts;
a gate dielectric cap over the gate structure and having a bottom surface below top surfaces of the source/drain contacts, wherein the gate dielectric cap has a lower portion below top surfaces of the gate spacers;
an oxide-based etch-resistant layer over the gate dielectric cap, wherein the oxide-based etch-resistant layer is separated from an interface between the gate dielectric cap and one of the gate spacers by a first distance, and the oxide-based etch-resistant layer is separated from a bottommost point of the gate dielectric cap by a second distance greater than the first distance;
a nitride-based etch stop layer over the oxide-based etch-resistant layer;
an interlayer dielectric (ILD) layer over the nitride-based etch stop layer; and
a via structure extending through the ILD layer, the nitride-based etch stop layer, and the oxide-based etch-resistant layer to electrically connect with the one of the source/drain contacts.
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