US 12,446,295 B2
Semiconductor device
Fei Zhou, Shanghai (CN)
Assigned to Semiconductor Manufacturing International (Shanghai) Corporation, Shanghai (CN); and Semiconductor Manufacturing International (Beijing) Corporation, Beijing (CN)
Filed by Semiconductor Manufacturing International (Shanghai) Corporation, Shanghai (CN); and Semiconductor Manufacturing International (Beijing) Corporation, Beijing (CN)
Filed on Dec. 20, 2022, as Appl. No. 18/085,210.
Application 18/085,210 is a division of application No. 16/857,447, filed on Apr. 24, 2020, granted, now 11,569,131.
Claims priority of application No. 201910336097.6 (CN), filed on Apr. 24, 2019.
Prior Publication US 2023/0118901 A1, Apr. 20, 2023
Int. Cl. H10D 84/03 (2025.01); H10D 30/01 (2025.01); H10D 30/62 (2025.01); H10D 64/01 (2025.01); H10D 64/23 (2025.01); H10D 84/01 (2025.01); H10D 84/83 (2025.01)
CPC H10D 84/038 (2025.01) [H10D 30/024 (2025.01); H10D 30/62 (2025.01); H10D 64/017 (2025.01); H10D 64/258 (2025.01); H10D 84/013 (2025.01); H10D 84/0147 (2025.01); H10D 84/0158 (2025.01); H10D 84/834 (2025.01)] 19 Claims
OG exemplary drawing
 
1. A semiconductor device, comprising:
a substrate;
a plurality of fins, formed on the substrate;
a dummy gate structure, formed across the plurality of fins and on the substrate;
a first sidewall spacer, formed on a sidewall of the dummy gate structure;
an interlayer dielectric layer, formed on a surface portion of each fin adjacent to the first sidewall spacer to cover a lower portion of a sidewall of the first sidewall spacer;
a second sidewall spacer, formed on a top of the interlayer dielectric layer and covering a remaining portion of the sidewall of the first sidewall spacer, wherein the top of the second sidewall spacer is coplanar with a top of the first sidewall spacer and the top of the dummy gate structure, and the interlayer dielectric layer isolates the second sidewall spacer from an adjacent fin of the plurality of fins; and
a source region and a drain region, formed in the fins on sides of the dummy gate structure, wherein each of the source region and the drain region is formed passing through an entire thickness of the interlayer dielectric layer that is located on the surface portion of each fin.
 
12. A semiconductor device, comprising: The device according
a substrate;
a plurality of fins, formed on the substrate;
a dummy gate structure, formed across the plurality of fins and on the substrate;
a first sidewall spacer, formed on a sidewall of the dummy gate structure;
an interlayer dielectric layer, formed on a surface portion of each fin adjacent to the first sidewall spacer to cover a lower portion of a sidewall of the first sidewall spacer; and
a second sidewall spacer, formed on a top of the interlayer dielectric layer and covering a remaining portion of the sidewall of the first sidewall spacer, wherein the top of the second sidewall spacer is coplanar with a top of the first sidewall spacer and the top of the dummy gate structure, and the interlayer dielectric layer isolates the second sidewall spacer from an adjacent fin of the plurality of fins, wherein:
the interlayer dielectric layer includes a portion formed in contact with a surface of the substrate and in the fin between the dummy gate structure and an adjacent dummy gate structure.