US 12,446,294 B2
Method of manufacturing semiconductor devices having different gate dielectric thickness within one transistor
Jen-Chun Chou, Taoyuan (TW); and Tung-Wen Cheng, New Taipei (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed by TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed on Jul. 26, 2022, as Appl. No. 17/874,279.
Application 17/874,279 is a division of application No. 16/654,457, filed on Oct. 16, 2019, granted, now 11,424,165.
Prior Publication US 2022/0375796 A1, Nov. 24, 2022
Int. Cl. H10D 84/03 (2025.01); H01L 21/762 (2006.01); H10D 30/01 (2025.01); H10D 30/62 (2025.01); H10D 84/01 (2025.01); H10D 84/83 (2025.01)
CPC H10D 84/038 (2025.01) [H01L 21/76224 (2013.01); H10D 30/024 (2025.01); H10D 30/6211 (2025.01); H10D 84/0144 (2025.01); H10D 84/0151 (2025.01); H10D 84/0158 (2025.01); H10D 84/834 (2025.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor device, comprising:
a first fin structure and a second fin structure disposed over a substrate;
an isolation insulating layer, an upper portion of the first and second fin structures protruding from the isolation insulating layer;
a first dielectric layer disposed on a lower part of the upper portion of the first fin structure and disposed on a lower part and an upper part of the upper portion of the second fin structure;
a second dielectric layer disposed on an upper part of the upper portion of the first fin structure;
a first gate electrode disposed over the first and second dielectric layers disposed on the first fin structure; and
a second gate electrode disposed over the first dielectric layer disposed on the second fin structure,
wherein a thickness of the second dielectric layer is smaller than a thickness of the first dielectric layer disposed over the first fin structure and the second fin structure, and
wherein a height of the upper part of the upper portion is 40% to 60% of a height of the upper portion of the first and second fin structures measured from an upper surface of the isolation insulating layer to an uppermost surface of the first and second fin structures.