US 12,446,292 B2
Semiconductor device and methods of formation
Keng-Wei Lin, New Taipei (TW); Chia-Chi Yu, New Taipei (TW); Chun-Lung Ni, Tainan (TW); and Jui Fu Hsieh, Zhubei (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Feb. 10, 2022, as Appl. No. 17/650,553.
Prior Publication US 2023/0253253 A1, Aug. 10, 2023
Int. Cl. H01L 21/32 (2006.01); H01L 21/3213 (2006.01); H01L 21/762 (2006.01); H10D 30/01 (2025.01); H10D 30/62 (2025.01); H10D 64/01 (2025.01); H10D 84/01 (2025.01); H10D 84/03 (2025.01)
CPC H10D 84/038 (2025.01) [H01L 21/32137 (2013.01); H01L 21/762 (2013.01); H10D 30/024 (2025.01); H10D 30/6211 (2025.01); H10D 64/017 (2025.01); H10D 84/013 (2025.01); H10D 84/0158 (2025.01)] 20 Claims
OG exemplary drawing
 
1. A method, comprising:
forming, to a first depth and using a first etch technique, a recess in a portion of a dummy gate structure of a semiconductor device,
wherein the first etch technique comprises an isotropic etch technique;
forming, to a second depth and using a second etch technique, the recess in the portion of the dummy gate structure,
wherein the second etch technique comprises an anisotropic etch technique; and
forming, after forming the recess to the second depth, a continuous polysilicon on oxide definition edge (CPODE) structure in the recess.