US 12,446,291 B2
Inverted top-tier FET for multi-tier gate-on-gate 3-dimension integration (3Di)
Daniel Chanemougame, Albany, NY (US); Lars Liebmann, Albany, NY (US); Jeffrey Smith, Albany, NY (US); Paul Gutwin, Albany, NY (US); and Xiaoqing Xu, Austin, TX (US)
Assigned to TOKYO ELECTRON LIMITED, Tokyo (JP)
Filed by TOKYO ELECTRON LIMITED, Tokyo (JP)
Filed on Dec. 3, 2021, as Appl. No. 17/542,024.
Claims priority of provisional application 63/151,166, filed on Feb. 19, 2021.
Prior Publication US 2022/0271033 A1, Aug. 25, 2022
Int. Cl. H10D 84/01 (2025.01); H01L 21/02 (2006.01); H01L 23/528 (2006.01); H10D 30/01 (2025.01); H10D 30/67 (2025.01); H10D 62/10 (2025.01); H10D 84/03 (2025.01); H10D 84/85 (2025.01); H10D 88/00 (2025.01)
CPC H10D 84/0186 (2025.01) [H01L 21/0259 (2013.01); H01L 23/5286 (2013.01); H10D 30/031 (2025.01); H10D 30/6735 (2025.01); H10D 30/6757 (2025.01); H10D 62/118 (2025.01); H10D 84/0167 (2025.01); H10D 84/038 (2025.01); H10D 84/856 (2025.01)] 18 Claims
OG exemplary drawing
 
1. A multi-tier semiconductor structure, comprising:
a first semiconductor device tier that includes first semiconductor devices;
a first signal wiring structure formed over and electrically connected to the first semiconductor device tier;
an insulator layer formed over the first signal wiring structure;
a second semiconductor device tier formed over the insulator layer, the second semiconductor device tier including second semiconductor devices;
a second signal wiring structure formed over and electrically connected to the second semiconductor device tier;
a second power rail that is formed over and electrically connected to the second semiconductor device tier; and
an inter-tier via formed vertically through the insulator layer and electrically connecting the second signal wiring structure to the first signal wiring structure,
wherein the inter-tier via has two opposing ends that are in direct contact with the second signal wiring structure and the first signal wiring structure, respectively,
the inter-tier via is electrically connected to a lower surface of the second signal wiring structure in a region that is above the second semiconductor device tier, and
the second power rail does not horizontally overlap with the region.