US 12,446,290 B2
Asymmetric gate extension in stacked FET
Ruilong Xie, Niskayuna, NY (US); Brent A. Anderson, Jericho, VT (US); Junli Wang, Slingerlands, NY (US); Jay William Strane, Wappingers Falls, NY (US); and Albert M. Chu, Nashua, NH (US)
Assigned to International Business Machines Corporation, Armonk, NY (US)
Filed by INTERNATIONAL BUSINESS MACHINES CORPORATION, Armonk, NY (US)
Filed on Apr. 18, 2023, as Appl. No. 18/302,021.
Prior Publication US 2024/0355679 A1, Oct. 24, 2024
Int. Cl. H10D 84/01 (2025.01); H10D 84/03 (2025.01); H10D 84/83 (2025.01); H10D 88/00 (2025.01)
CPC H10D 84/0142 (2025.01) [H10D 84/038 (2025.01); H10D 84/83 (2025.01); H10D 88/01 (2025.01)] 20 Claims
OG exemplary drawing
 
16. A semiconductor structure comprising:
a first stack of transistors with a first transistor on top of a second transistor, wherein a gate of the first transistor has a first width, and a gate of the second transistor has a second width, with the first width being narrower than the second width; and
a second stack of transistors with a third transistor on top of a fourth transistor, wherein a gate of the third transistor has a third width, and a gate of the fourth transistor has a fourth width, with the third width being narrower than the fourth width,
wherein the first and the second transistor respectively have a first gate extension at a first side of the first stack and a second gate extension at a second side of the first stack, the first gate extension being narrower than the second gate extension, and wherein the third and the fourth transistor respectively have a third gate extension at a first side of the second stack and a fourth gate extension at a second side of the second stack, the third gate extension being narrower than the fourth gate extension.