| CPC H10D 64/513 (2025.01) [H10D 30/6211 (2025.01)] | 23 Claims |
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1. A semiconductor device, comprising:
an isolation layer formed to define active regions including active fins in a substrate;
gate trenches extending across the active fins and the isolation layer; and
buried gates that fill the gate trenches, and include
fin gates disposed on sidewalls of the active fins,
active gates disposed over the active fins, and
passing gates disposed over the isolation layer,
wherein bottom surfaces of the passing gates are disposed at a higher level than bottom surfaces of the active gates, and
bottom surfaces of the fin gates are disposed at a lower level than the bottom surfaces of the active gates.
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