US 12,446,287 B2
Semiconductor device and method for manufacturing the same
Yang Liu, Suzhou (CN); Liang Chen, Suzhou (CN); Xiao Zhang, Suzhou (CN); Haoning Zheng, Suzhou (CN); and King Yuen Wong, Suzhou (CN)
Assigned to INNOSCIENCE (SUZHOU) SEMICONDUCTOR CO., LTD., Suzhou (CN)
Appl. No. 17/775,879
Filed by INNOSCIENCE (SUZHOU) SEMICONDUCTOR CO., LTD., Suzhou (CN)
PCT Filed Mar. 29, 2022, PCT No. PCT/CN2022/083542
§ 371(c)(1), (2) Date May 10, 2022,
PCT Pub. No. WO2023/184129, PCT Pub. Date Oct. 5, 2023.
Prior Publication US 2024/0154012 A1, May 9, 2024
Int. Cl. H01L 29/423 (2006.01); H01L 29/20 (2006.01); H01L 29/40 (2006.01); H01L 29/66 (2006.01); H01L 29/778 (2006.01); H10D 30/01 (2025.01); H10D 30/47 (2025.01); H10D 62/85 (2025.01); H10D 64/01 (2025.01); H10D 64/27 (2025.01)
CPC H10D 64/411 (2025.01) [H10D 30/015 (2025.01); H10D 30/475 (2025.01); H10D 62/8503 (2025.01); H10D 64/01 (2025.01)] 19 Claims
OG exemplary drawing
 
1. A semiconductor device, comprising:
a first nitride-based semiconductor layer;
a second nitride-based semiconductor layer disposed over the first nitride-based semiconductor layer, wherein the second nitride-based semiconductor layer has a bandgap greater than that of the first nitride-based semiconductor layer; and
a gate structure disposed over the first nitride-based semiconductor layer, wherein the gate structure comprises:
an outer spacer disposed over the second nitride-based semiconductor layer and having at least two opposite inner sidewalls to define a gate trench;
an inner spacer disposed over the first nitride-based semiconductor layer and within the gate trench; and
a gate electrode disposed in the gate trench and covered by the inner spacer, wherein the at least inner spacer and the gate electrode extend downward to collaboratively form a bottom portion of the gate structure with a first width greater than a second width of a bottom surface of the gate electrode,
wherein the semiconductor device further comprises a doped nitride-based semiconductor layer at least abutting against the outer spacer, wherein an entirety of a bottom surface of the doped nitride-based semiconductor layer is in a position under the inner spacer.