| CPC H10D 64/112 (2025.01) [H01L 21/32155 (2013.01); H10D 30/0281 (2025.01); H10D 30/65 (2025.01); H10D 62/154 (2025.01); H10D 62/158 (2025.01)] | 20 Claims |
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1. A semiconductor device, comprising:
a semiconductor substrate, comprising a drift region in a first conductivity type and a well region in a second conductivity type, wherein an end of the drift region away from the well region is arranged with a drain region, and an end of the well region away from the drift region is arranged with a source region;
a gate oxide layer, arranged on the semiconductor substrate and disposed between the source region and the drain region; and
a polysilicon field plate, arranged on the gate oxide layer,
wherein at least a portion of the polysilicon field plate is projected onto the drift region, and the portion of the polysilicon field plate that is projected onto the drift region comprises at least two field-plate regions having different doping concentrations; in a direction from an end of the drift region near the well region approaching the drain region, the doping concentrations of the portion of the polysilicon field plate projected onto the drift region gradually decrease; and
while the semiconductor device is operating, in the direction from the end of the drift region near the well region approaching the drain region, an equivalent electrical thickness of an insulating layer between the portion of the polysilicon field plate projected onto the drift region and the drift region for forming a field plate capacitor gradually increases.
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