US 12,446,285 B2
Group III nitride-based transistor device
Helmut Brech, Lappersdorf (DE); and John Twynam, Regensburg (DE)
Assigned to Infineon Technologies AG, Neubiberg (DE)
Appl. No. 17/921,781
Filed by Infineon Technologies AG, Neubiberg (DE)
PCT Filed Apr. 28, 2021, PCT No. PCT/EP2021/061165
§ 371(c)(1), (2) Date Oct. 27, 2022,
PCT Pub. No. WO2021/219740, PCT Pub. Date Nov. 4, 2021.
Claims priority of application No. 20171930 (EP), filed on Apr. 28, 2020.
Prior Publication US 2023/0170393 A1, Jun. 1, 2023
Int. Cl. H10D 30/47 (2025.01); H01L 21/765 (2006.01); H01L 23/29 (2006.01); H01L 23/31 (2006.01); H10D 30/01 (2025.01); H10D 62/824 (2025.01); H10D 62/85 (2025.01); H10D 64/00 (2025.01); H10D 64/01 (2025.01)
CPC H10D 64/111 (2025.01) [H01L 21/765 (2013.01); H01L 23/291 (2013.01); H01L 23/3171 (2013.01); H10D 30/015 (2025.01); H10D 30/475 (2025.01); H10D 30/4755 (2025.01); H10D 62/824 (2025.01); H10D 62/8503 (2025.01); H10D 64/01 (2025.01)] 22 Claims
OG exemplary drawing
 
1. A Group III nitride-based transistor device, comprising:
a source electrode, a drain electrode and a gate electrode positioned on a first major surface of a Group III nitride based-based layer, wherein the gate electrode is laterally arranged between the source electrode and the drain electrode;
a passivation layer arranged on the first major surface; and
a field plate electrically connected to the source electrode, the field plate having a lower surface arranged on the passivation layer, the field plate being laterally arranged between, and laterally spaced apart from, the gate electrode and the drain electrode,
wherein the Group III nitride-based transistor device has a gate drain capacitance (CGD), a drain source capacitance (CDS), and a drain source on resistance (RDSon),
wherein a ratio of the gate drain capacitance (CGD) at a drain source voltage (VDS) of 0V and the gate drain capacitance CGD at a value of VDS>0V is at least 3:1, wherein VDS is less than 15V.