US 12,446,279 B2
Semiconductor device having 2D channel layer
Yun-Yuan Wang, Kaohsiung (TW); Chih-Hsiang Hsiao, Taoyuan (TW); I-Chih Ni, New Taipei (TW); and Chih-I Wu, Taipei (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., Hsinchu (TW); and NATIONAL TAIWAN UNIVERSITY, Taipei (TW)
Filed by TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., Hsinchu (TW); and NATIONAL TAIWAN UNIVERSITY, Taipei (TW)
Filed on Nov. 20, 2023, as Appl. No. 18/515,148.
Application 18/515,148 is a continuation of application No. 17/827,543, filed on May 27, 2022, granted, now 11,855,150.
Application 17/827,543 is a continuation of application No. 16/721,752, filed on Dec. 19, 2019, granted, now 11,362,180, issued on Jun. 14, 2022.
Prior Publication US 2024/0088228 A1, Mar. 14, 2024
Int. Cl. H10D 62/17 (2025.01); H10D 62/13 (2025.01); H10D 64/01 (2025.01); H10D 64/20 (2025.01)
CPC H10D 62/307 (2025.01) [H10D 62/149 (2025.01); H10D 64/01 (2025.01); H10D 64/20 (2025.01)] 20 Claims
OG exemplary drawing
 
1. A device, comprising:
a substrate;
a chalcogenide channel layer over the substrate;
a top chalcogenide barrier layer over the chalcogenide channel layer, wherein a dopant concentration of the top chalcogenide barrier layer is greater than a dopant concentration of the chalcogenide channel layer, and the top chalcogenide barrier layer has an energy band gap greater than an energy band gap of the chalcogenide channel layer;
a chalcogenide spacer layer between and in contact with the chalcogenide channel layer and the top chalcogenide barrier layer, wherein the chalcogenide spacer layer and the top chalcogenide barrier layer comprise same materials, and a dopant concentration of the chalcogenide spacer layer is lower than the dopant concentration of the top chalcogenide barrier layer;
source/drain contacts over the chalcogenide channel layer; and
a gate electrode over the substrate.