US 12,446,272 B2
Semiconductor devices and methods of manufacturing semiconductor devices
Jimmy Robert Hannes Franchi, Enköping (SE); and Martin Domeij, Sollentuna (SE)
Assigned to SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC, Scottsdale, AZ (US)
Filed by SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC, Phoenix, AZ (US)
Filed on Nov. 28, 2022, as Appl. No. 18/058,915.
Prior Publication US 2024/0178269 A1, May 30, 2024
Int. Cl. H10D 62/10 (2025.01); H01L 21/04 (2006.01); H10D 12/01 (2025.01); H10D 30/66 (2025.01); H10D 62/17 (2025.01); H10D 62/832 (2025.01)
CPC H10D 62/109 (2025.01) [H01L 21/0465 (2013.01); H10D 12/031 (2025.01); H10D 30/66 (2025.01); H10D 62/393 (2025.01); H10D 62/8325 (2025.01)] 17 Claims
OG exemplary drawing
 
1. A method for manufacturing a semiconductor device, comprising:
providing a body of semiconductor material comprising:
a substrate; and
a semiconductor region over the substrate and comprising a first conductivity type, wherein the semiconductor region comprises a first side of the body of semiconductor and the substrate comprises a second side of the body of semiconductor material opposite to the first side;
providing a first doped region comprising the first conductivity type within the semiconductor region, wherein the first doped region provides a first JFET channel region for a first JFET device;
providing a first mask over the first side comprising a first opening above the first doped region;
providing a second doped region comprising a second conductivity type opposite to the first conductivity type within the first doped region, wherein the second doped region provides a body region for a MOSFET device, a gate region for the first JFET device, and a first JFET gate for a second JFET device;
providing a first spacer structure within the first opening to define a second opening smaller than the first opening;
providing a third doped region comprising the first conductivity type within the second doped region aligned to the second opening, wherein the third doped region provides a second JFET channel region for the second JFET device, a first JFET source for the first JFET device, and a JFET drain for the second JFET device;
providing a second spacer structure adjacent to the first spacer structure within the second opening to define a third opening smaller than the second opening;
providing a fourth doped region of the second conductivity type within the third doped region aligned with the third opening, wherein the fourth doped region provides a second JFET gate for the second JFET device;
providing a fifth doped region comprising the first conductivity type adjacent to the fourth doped region, wherein the fifth doped region provides a source for the MOSFET device and a second JFET source for the second JFET device; and
providing a sixth doped region comprising the second conductivity type extending through a portion of the fifth doped region and coupled to the second doped region, wherein the sixth doped region provides a body contact for the MOSFET device and a gate contact to the first JFET gate for the second JFET device.