| CPC H10D 62/021 (2025.01) [H10D 30/014 (2025.01); H10D 30/43 (2025.01); H10D 30/6729 (2025.01); H10D 30/6757 (2025.01); H10D 62/121 (2025.01); H10D 64/017 (2025.01); H10D 84/013 (2025.01); H10D 84/0158 (2025.01); H10D 84/038 (2025.01)] | 20 Claims |

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8. A semiconductor device structure, comprising:
a first source/drain (S/D) region disposed over a substrate;
a second S/D region disposed over the substrate;
a dielectric wall disposed between the first and second S/D regions;
a first conductive contact disposed over and electrically connected to the first S/D region;
a second conductive contact disposed over and electrically connected to the second S/D region;
a first dielectric material disposed between the first and second conductive contacts, wherein the first dielectric material has a top surface substantially coplanar with a top surface of the first conductive contact, and the first dielectric material extends to a level located below a bottom surface of the first conductive contact; and
an interlayer dielectric (ILD) layer disposed under the first conductive contact, wherein the first dielectric material and the ILD layer comprise different materials.
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