| CPC H10D 30/83 (2025.01) [H10D 12/031 (2025.01); H10D 62/8325 (2025.01)] | 19 Claims |
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1. A structure for a junction field-effect transistor, the structure comprising:
a semiconductor substrate including a bulk substrate, a semiconductor layer on the bulk substrate, and a first trench in the semiconductor layer, the semiconductor substrate having a first surface, the bulk substrate and the semiconductor layer comprising a wide bandgap semiconductor material having a first conductivity type;
a source including a first doped region in the semiconductor layer adjacent to the first trench, the first doped region having the first conductivity type, and the first doped region having a first boundary adjacent to the first surface of the semiconductor substrate and a second boundary spaced in depth from the first boundary;
a first gate structure including a first conductor layer inside the first trench and a first dielectric layer inside the first trench, the first conductor layer having a second surface positioned between the first boundary of the first doped region and the second boundary of the first doped region, and the first dielectric layer positioned on the second surface of the first conductor layer; and
a first junction termination extension including a plurality of doped regions in the semiconductor layer adjacent to the first trench, the plurality of doped regions of the first junction termination extension having a second conductivity type opposite from the first conductivity type,
wherein the first trench is positioned in a lateral direction between the first doped region of the source and the plurality of doped regions of the first junction termination extension, and the plurality of doped regions of the first junction termination extension have a width dimension that alternates between a maximum width and a minimum width with increasing depth in the semiconductor layer below the first surface.
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