US 12,446,269 B2
Strained nanosheets on silicon-on-insulator substrate
Ding-Kang Shih, New Taipei (TW); Chung-Liang Cheng, Changhua County (TW); and Pang-Yen Tsai, Jhu-bei (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on May 6, 2022, as Appl. No. 17/738,759.
Claims priority of provisional application 63/227,466, filed on Jul. 30, 2021.
Prior Publication US 2023/0031490 A1, Feb. 2, 2023
Int. Cl. H10D 30/69 (2025.01); H01L 21/02 (2006.01); H10D 30/01 (2025.01); H10D 30/67 (2025.01); H10D 62/10 (2025.01); H10D 86/00 (2025.01); H10D 86/01 (2025.01)
CPC H10D 30/798 (2025.01) [H01L 21/02532 (2013.01); H01L 21/0259 (2013.01); H10D 30/031 (2025.01); H10D 30/6735 (2025.01); H10D 30/6757 (2025.01); H10D 62/118 (2025.01); H10D 86/01 (2025.01); H10D 86/201 (2025.01)] 20 Claims
OG exemplary drawing
 
1. A method, comprising:
forming a trench in a silicon (Si) substrate;
filling the trench with strained silicon germanium (SiGe) to form a Si/SiGe bi-layer;
forming a viscous layer over the Si/SiGe bi-layer;
inverting the silicon substrate;
bonding the viscous layer to a carrier wafer; and
relaxing the strained SiGe so that the Si/SiGe bi-layer has a silicon portion and a strain-relaxed SiGe portion.