| CPC H10D 30/701 (2025.01) [H10B 51/30 (2023.02); H10D 30/0415 (2025.01); H10D 64/033 (2025.01); H10D 64/689 (2025.01)] | 20 Claims |
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1. A ferroelectric transistor (FeFET) memory device comprising:
a metal gate;
a gate dielectric layer adjacent to the metal gate;
a semiconductor channel layer adjacent to the gate dielectric layer;
a metal drain electrode; and
a metal source electrode recessed into the semiconductor channel layer,
wherein the metal gate is vertically spaced apart from the semiconductor channel layer, the metal source electrode, and the metal drain electrode by the gate dielectric layer.
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