US 12,446,265 B2
Semiconductor devices and methods for manufacturing the same, and NAND memory devices
Lan Yao, Wuhan (CN); Ziqun Hua, Wuhan (CN); and Yanwei Shi, Wuhan (CN)
Assigned to YANGTZE MEMORY TECHNOLOGIES CO., LTD., Wuhan (CN)
Filed by YANGTZE MEMORY TECHNOLOGIES CO., LTD., Wuhan (CN)
Filed on Aug. 5, 2022, as Appl. No. 17/882,115.
Application 17/882,115 is a continuation of application No. PCT/CN2021/115849, filed on Aug. 31, 2021.
Prior Publication US 2023/0067170 A1, Mar. 2, 2023
Int. Cl. H10D 30/68 (2025.01); G11C 16/04 (2006.01); H01L 21/762 (2006.01); H10B 41/10 (2023.01); H10B 41/27 (2023.01); H10B 41/35 (2023.01); H10B 41/41 (2023.01); H10B 43/10 (2023.01); H10B 43/27 (2023.01); H10B 43/35 (2023.01); H10B 43/40 (2023.01); H10D 30/01 (2025.01); H10D 30/69 (2025.01); H10D 64/01 (2025.01)
CPC H10D 30/6894 (2025.01) [G11C 16/0483 (2013.01); H01L 21/76224 (2013.01); H10B 41/10 (2023.02); H10B 41/35 (2023.02); H10B 41/41 (2023.02); H10B 43/10 (2023.02); H10B 43/35 (2023.02); H10B 43/40 (2023.02); H10D 30/0411 (2025.01); H10D 30/0413 (2025.01); H10D 30/68 (2025.01); H10D 30/69 (2025.01); H10D 30/699 (2025.01); H10D 64/035 (2025.01); H10D 64/037 (2025.01); H10B 41/27 (2023.02); H10B 43/27 (2023.02)] 20 Claims
OG exemplary drawing
 
1. A semiconductor device, comprising:
a substrate comprising a first active region, a second active region, and an isolation region surrounding the first active region, the first active region comprising a first channel region sandwiched between a first source region and a first drain region in a lateral direction, the first active region and the second active region are separated by the isolation region, and the second active region comprising a second channel region sandwiched between a second source region and a second drain region in the lateral direction;
a first groove located between the isolation region and the first channel region, the first groove being partially located in the isolation region without penetrating the isolation region;
a second groove located between the isolation region and the second channel region, the second groove being partially located in the isolation region without penetrating the isolation region;
a first gate insulating layer covering the first groove and the first channel region;
a second gate insulating layer covering the second groove and the second channel region, a thickness of the second gate insulating layer being different from a thickness of the first gate insulating layer; and
a first gate located on the first gate insulating layer, and covering the first channel region and filling the first groove.