US 12,446,264 B2
Complementary field effect transistor (CFET) with balanced N and P drive current
Xia Li, San Diego, CA (US); Junjing Bao, San Diego, CA (US); and Giridhar Nallapati, San Diego, CA (US)
Assigned to QUALCOMM INCORPORATED, San Diego, CA (US)
Filed by QUALCOMM Incorporated, San Diego, CA (US)
Filed on Dec. 20, 2022, as Appl. No. 18/068,992.
Prior Publication US 2024/0204109 A1, Jun. 20, 2024
Int. Cl. H10D 84/00 (2025.01); H10D 30/01 (2025.01); H10D 30/43 (2025.01); H10D 30/67 (2025.01); H10D 64/01 (2025.01); H10D 84/01 (2025.01); H10D 84/03 (2025.01); H10D 84/85 (2025.01); H10D 62/10 (2025.01)
CPC H10D 30/6757 (2025.01) [H10D 30/014 (2025.01); H10D 30/43 (2025.01); H10D 30/6729 (2025.01); H10D 30/6735 (2025.01); H10D 64/01 (2025.01); H10D 84/0167 (2025.01); H10D 84/0186 (2025.01); H10D 84/038 (2025.01); H10D 84/85 (2025.01); H10D 62/121 (2025.01); H10D 64/017 (2025.01); H10D 64/018 (2025.01)] 18 Claims
OG exemplary drawing
 
1. A complementary field effect transistor (CFET) structure, comprising:
an n-channel field effect transistor (nFET) having a plurality of horizontal p-doped nanosheet channels arranged in parallel in a first vertical stack and separated from each other by a first vertical distance (D1), each horizontal p-doped nanosheet channel having a first width (W1), and connecting a first source contact to a first drain contact through a first gate-all-around (GAA) region having a first length (L1) and being connected to a first gate contact; and
a p-channel field effect transistor (pFET) having a plurality of horizontal n-doped nanosheet channels arranged in parallel in a second vertical stack and separated from each other by a second vertical distance (D2), each horizontal n-doped nanosheet channel having a second width (W2), and connecting a second source contact to a second drain contact through a second GAA region having a second length (L2) and being connected to a second gate contact,
wherein the first vertical stack is disposed on the second vertical stack, and wherein W2/L2 is not equal to W1/L1, and
wherein the first source contact, the first gate contact, and the first drain contact are disposed on a first surface of the CFET structure and the second source contact, the second gate contact, and the second drain contact are disposed on a second surface of the CFET structure opposite the first surface of the CFET structure.