| CPC H10D 30/6735 (2025.01) [H10D 30/43 (2025.01); H10D 30/6757 (2025.01); H10D 62/121 (2025.01); H10D 64/017 (2025.01)] | 20 Claims |
|
1. A semiconductor device comprising:
a substrate comprising an active region extending in a first direction;
a gate structure extending in a second direction and intersecting the active region, on the substrate;
a plurality of channel layers on the active region, spaced apart from each other in a third direction perpendicular to an upper surface of the substrate, and surrounded by the gate structure; and
a source/drain region on the active region adjacent the gate structure and connected to the plurality of channel layers,
wherein the source/drain region comprises:
a first semiconductor layer on side surfaces of the plurality of channel layers;
a diffusion barrier layer on an upper region of the first semiconductor layer and comprising carbon, wherein an upper surface of a first channel layer that is a lowermost channel layer among the plurality of channel layers is provided between the substrate and a lower end of the diffusion barrier layer; and
a second semiconductor layer on the diffusion barrier layer and the first semiconductor layer.
|