US 12,446,255 B2
Semiconductor structure with source/drain multi-layer structure and method for forming the same
Chun-Chieh Wang, Kaohsiung (TW); Yu-Ting Lin, Tainan (TW); Yueh-Ching Pai, Taichung (TW); Shih-Chieh Chang, Taipei (TW); and Huai-Tei Yang, Hsin-Chu (TW)
Assigned to Parabellum Strategic Oppurtunities Fund LLC, Austin, TX (US)
Filed by Parabellum Strategic Opportunities Fund LLC, Wilmington, DE (US)
Filed on Apr. 17, 2024, as Appl. No. 18/637,874.
Application 18/637,874 is a continuation of application No. 18/063,711, filed on Dec. 9, 2022, granted, now 11,990,550.
Application 18/063,711 is a continuation of application No. 17/155,467, filed on Jan. 22, 2021, granted, now 11,527,655, issued on Dec. 13, 2022.
Application 17/155,467 is a continuation of application No. 16/654,175, filed on Oct. 16, 2019, granted, now 10,937,910, issued on Mar. 2, 2021.
Application 16/654,175 is a continuation of application No. 16/043,371, filed on Jul. 24, 2018, granted, now 10,468,530, issued on Nov. 5, 2019.
Claims priority of provisional application 62/586,272, filed on Nov. 15, 2017.
Prior Publication US 2024/0266439 A1, Aug. 8, 2024
Int. Cl. H10D 30/62 (2025.01); H01L 21/02 (2006.01); H01L 21/3065 (2006.01); H01L 21/3105 (2006.01); H01L 21/311 (2006.01); H01L 21/32 (2006.01); H01L 21/768 (2006.01); H10D 30/01 (2025.01); H10D 62/10 (2025.01); H10D 62/13 (2025.01); H10D 64/01 (2025.01); H10D 84/01 (2025.01); H10D 84/03 (2025.01); H10D 84/83 (2025.01)
CPC H10D 30/6217 (2025.01) [H01L 21/0217 (2013.01); H01L 21/0228 (2013.01); H01L 21/3065 (2013.01); H01L 21/3105 (2013.01); H01L 21/31116 (2013.01); H01L 21/32 (2013.01); H01L 21/76897 (2013.01); H10D 30/024 (2025.01); H10D 30/0241 (2025.01); H10D 62/115 (2025.01); H10D 62/151 (2025.01); H10D 64/018 (2025.01); H10D 84/0158 (2025.01); H10D 84/0193 (2025.01); H10D 84/038 (2025.01); H10D 84/834 (2025.01); H10D 64/017 (2025.01); H10D 84/017 (2025.01)] 16 Claims
OG exemplary drawing
 
1. A semiconductor structure, comprising:
a gate structure formed over a fin structure;
a gate spacer layer formed on a sidewall surface of the gate structure;
a source/drain (S/D) epitaxial layer formed adjacent to the gate structure in a recess of the fin structure, wherein the S/D epitaxial layer comprises a first S/D epitaxial layer and a second S/D epitaxial layer, and there is a step height between a top surface of the second epitaxial layer and a top surface of the first epitaxial layer, wherein a thickness of the second S/D epitaxial layer is greater than a thickness of the first S/D epitaxial layer, and wherein the gate spacer layer is formed over a top surface of the S/D epitaxial layer;
a dielectric spacer layer formed on the S/D epitaxial layer;
a contact plug barrier formed over the S/D epitaxial layer; and
a contact plug surrounded by the contact plug barrier, wherein the contact plug is separated from the gate spacer layer by the dielectric spacer layer and the contact plug barrier.