| CPC H10D 30/611 (2025.01) [H01L 21/2252 (2013.01); H01L 21/28114 (2013.01); H01L 21/28518 (2013.01); H01L 21/743 (2013.01); H10D 30/023 (2025.01); H10D 62/371 (2025.01); H10D 62/378 (2025.01); H10D 64/01 (2025.01); H10D 64/021 (2025.01); H10D 64/518 (2025.01); H10D 64/62 (2025.01)] | 14 Claims |
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1. A structure comprising:
an insulator layer on a semiconductor substrate;
above the insulator layer, source/drain regions and a section of a semiconductor layer extending laterally between the source/drain regions, wherein the section of the semiconductor layer has end portions adjacent to the source/drain regions and a center portion positioned laterally between the end portions;
a primary gate structure comprising: the insulator layer and a well region in the semiconductor substrate adjacent to the insulator layer opposite at least the section of the semiconductor layer extending laterally between the source/drain regions; and
at least one secondary gate structure on at least one of the end portions,
wherein the at least one secondary gate structure is offset from the center portion and from an adjacent source/drain region of the source/drain regions,
wherein the at least one secondary gate structure comprises two secondary gate structures on the end portions, respectively, adjacent to the source/drain regions, and
wherein the structure further comprises:
inner and outer gate sidewall spacers on the secondary gate structures;
a dielectric layer immediately adjacent to and covering the center portion and further extending partially over the secondary gate structures; and
interlayer dielectric material on the dielectric layer.
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