US 12,446,252 B2
Transistors including semiconductor surface modification and related fabrication methods
Joshua Bisges, Wake Forest, NC (US); Kyle Bothe, Cary, NC (US); and Matthew King, Wake Forest, NC (US)
Assigned to MACOM Technology Solutions Holdings, Inc., Lowell, MA (US)
Filed by MACOM Technology Solutions Holdings, Inc., Lowell, MA (US)
Filed on May 20, 2021, as Appl. No. 17/325,488.
Prior Publication US 2022/0376104 A1, Nov. 24, 2022
Int. Cl. H10D 30/47 (2025.01); H01L 21/263 (2006.01); H10D 62/17 (2025.01); H10D 62/824 (2025.01); H10D 64/00 (2025.01)
CPC H10D 30/4755 (2025.01) [H01L 21/263 (2013.01); H10D 62/221 (2025.01); H10D 62/824 (2025.01); H10D 64/111 (2025.01)] 34 Claims
OG exemplary drawing
 
1. A transistor device, comprising:
a semiconductor structure comprising a channel layer and a barrier layer defining a heterojunction therebetween;
source and drain contacts on the semiconductor structure;
a gate on the semiconductor structure between the source and drain contacts; and
a surface passivation layer directly on the barrier layer of the semiconductor structure between the gate and one of the source contact or the drain contact, the surface passivation layer comprising a first opening therein that exposes a first region of the semiconductor structure and a second opening having the gate therein,
wherein the first region is between the gate and the one of the source contact or the drain contact, is laterally spaced apart from the source and drain contacts, and comprises a greater surface potential and has a higher conductivity than a second region of the semiconductor structure adjacent the gate.