| CPC H10D 30/475 (2025.01) [H10D 1/62 (2025.01); H10D 62/8503 (2025.01); H10D 64/111 (2025.01); H10D 84/811 (2025.01); H10D 64/62 (2025.01)] | 10 Claims |
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1. A semiconductor device comprising:
a drift region formed laterally between a gate and a drain, wherein the drift region is configured to support an electric field;
a plurality of field plates disposed above the drift region, the plurality of field plates comprising:
a first field plate configured to support a first potential;
a second field plate configured to support a second potential; and
a third field plate configured to support a third potential;
a capacitance network electrically coupled to the plurality of field plates, wherein the capacitance network is configured to establish the first potential and the second potential so as to distribute the electric field, the capacitance network comprising:
a first capacitor electrically coupled to the first field plate;
a second capacitor electrically coupled to the second field plate; and
a third capacitor electrically coupled between a direct current (DC) potential and the third field plate; and
a discharge network comprising a plurality of field effect transistors electrically coupled to the plurality of field plates, the plurality of field effect transistors comprising:
a first field effect transistor electrically coupled between the DC potential and the first field plate;
a second field effect transistor electrically coupled between the drain and the second field plate;
a third field effect transistor electrically coupled between the first field plate and the third field plate, and
a fourth field effect transistor electrically coupled between the third field plate and the second field plate.
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