US 12,446,244 B2
Semiconductor structure and manufacturing method thereof
Kai Cheng, Jiangsu (CN); and Peng Xiang, Jiangsu (CN)
Assigned to ENKRIS SEMICONDUCTOR, INC., Jiangsu (CN)
Appl. No. 18/010,915
Filed by ENKRIS SEMICONDUCTOR, INC., Jiangsu (CN)
PCT Filed Nov. 6, 2020, PCT No. PCT/CN2020/127246
§ 371(c)(1), (2) Date Dec. 16, 2022,
PCT Pub. No. WO2022/094966, PCT Pub. Date May 12, 2022.
Prior Publication US 2023/0238446 A1, Jul. 27, 2023
Int. Cl. H10D 30/01 (2025.01); H10D 30/47 (2025.01); H10D 62/10 (2025.01); H10D 62/85 (2025.01)
CPC H10D 30/015 (2025.01) [H10D 30/475 (2025.01); H10D 62/115 (2025.01); H10D 62/8503 (2025.01)] 14 Claims
OG exemplary drawing
 
1. A semiconductor structure, comprising:
a semiconductor substrate;
a plurality of stacked structures and a plurality of isolation structures on the semiconductor substrate, wherein the stacked structures are spaced apart each other, each of the isolation structures is located between adjacent stacked structures, each of the stacked structures comprises a nucleation layer and a first epitaxial layer from bottom to top; and
a heterojunction structure on the plurality of stacked structures, wherein the heterojunction structure is distributed over an entire surface, and an air gap is formed between the heterojunction structure and each of the isolation structures.