| CPC H10D 8/043 (2025.01) [H10D 8/411 (2025.01); H10D 62/106 (2025.01); H10D 62/129 (2025.01); H10D 62/60 (2025.01); H10D 62/142 (2025.01)] | 18 Claims |
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1. A power semiconductor device divided into an active cell region, an intermediate region surrounding the active cell region, and a terminal region surrounding the intermediate region in a plan view, the power semiconductor device comprising:
a semiconductor substrate having a first main surface and a second main surface facing each other;
a first metal layer provided on the first main surface of the semiconductor substrate; and
a second metal layer provided on the second main surface of the semiconductor substrate, wherein
the semiconductor substrate includes:
a drift layer of a first conductivity type;
a buffer layer of the first conductivity type provided between the drift layer and the second metal layer in the active cell region; and
at least one cathode layer of the first conductivity type provided between the buffer layer and the second metal layer in the active cell region while contacting the buffer layer and the second metal layer,
the cathode layer of the first conductivity type includes:
a first cathode layer having one impurity concentration peak point and contacting the second metal layer; and
a second cathode layer having one impurity concentration peak point and provided between the first cathode layer and the buffer layer while contacting the first cathode layer and the buffer layer,
crystal defect density in the first cathode layer is higher than crystal defect density in the second cathode layer, and
the cathode layer of the first conductivity type is absent in the intermediate region and the terminal region.
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