US 12,446,240 B2
Interconnect layout for semiconductor device
Chun-Hsiung Tsai, Xinpu Township (TW); Shahaji B. More, Hsinchu (TW); Yu-Ming Lin, Hsinchu (TW); and Clement Hsingjen Wann, Carmel, NY (US)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed on Feb. 23, 2024, as Appl. No. 18/585,211.
Application 18/585,211 is a continuation of application No. 17/549,389, filed on Dec. 13, 2021, granted, now 11,961,878.
Application 17/549,389 is a continuation of application No. 16/738,095, filed on Jan. 9, 2020, granted, now 11,201,205, issued on Dec. 14, 2021.
Claims priority of provisional application 62/880,753, filed on Jul. 31, 2019.
Prior Publication US 2024/0194730 A1, Jun. 13, 2024
Int. Cl. H01L 23/528 (2006.01); H01L 23/00 (2006.01); H01L 23/522 (2006.01); H10B 12/00 (2023.01); H10D 1/66 (2025.01); H10D 1/68 (2025.01); H10F 39/00 (2025.01)
CPC H10D 1/692 (2025.01) [H01L 23/5226 (2013.01); H01L 23/528 (2013.01); H01L 24/18 (2013.01); H01L 24/25 (2013.01); H10B 12/038 (2023.02); H10B 12/37 (2023.02); H10D 1/665 (2025.01); H10F 39/811 (2025.01); H01L 2224/821 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method comprising:
forming a recess in a substrate;
forming a doped region in the substrate, the recess being adjacent to the doped region;
at least partially forming a deep trench capacitor (DTC) in the recess; and forming an interconnect structure over the DTC and the substrate, wherein forming the interconnect structure comprises:
forming a seal ring structure in electrical contact with the doped region, wherein the recess is laterally offset from the seal ring structure;
forming a first conductive line in electrical contact with the DTC; and
forming a second conductive line over the first conductive line, wherein
the first conductive line electrically couples the second conductive line to the DTC, wherein
a portion of one of the first conductive line or the second conductive line is a part of the seal ring structure, wherein
the one of the first conductive line or the second conductive line is a part of a circuitry on the substrate.