| CPC H10B 80/00 (2023.02) [H10B 41/27 (2023.02); H10B 43/27 (2023.02)] | 20 Claims |
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1. A semiconductor device comprising:
a peripheral circuit structure comprising peripheral circuits on a semiconductor substrate and first bonding pads electrically connected to the peripheral circuits; and
a cell array structure comprising memory cells arranged three-dimensionally on a semiconductor layer and second bonding pads electrically connected to the memory cells and bonded to the first bonding pads,
wherein the cell array structure further comprises:
a stacked structure comprising insulating layers and electrodes alternately stacked on a first surface of the semiconductor layer;
an external connection pad on a lower insulating layer that extends on a second surface of the semiconductor layer;
a dummy pattern positioned at a same level as the semiconductor layer relative to the semiconductor substrate; and
a photosensitive insulating layer on the semiconductor layer and the dummy pattern,
wherein a first thickness of a portion of the photosensitive insulating layer vertically overlapping the external connection pad is greater than a second thickness of another portion of the photosensitive insulating layer vertically overlapping the dummy pattern.
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